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FEATURES
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LTC2600/LTC2610/LTC2620 Octal 16-/14-/12-Bit Rail-to-Rail DACs in 16-Lead SSOP DESCRIPTION
The LTC(R)2600/LTC2610/LTC2620 are octal 16-, 14- and 12-bit, 2.5V-to-5.5V rail-to-rail voltage-output DACs in 16-lead narrow SSOP and 20-lead 4mm x 5mm QFN packages. They have built-in high performance output buffers and are guaranteed monotonic. These parts establish new board-density benchmarks for 16- and 14-bit DACs and advance performance standards for output drive, crosstalk and load regulation in single-supply, voltage-output multiples. The parts use a simple SPI/MICROWIRE compatible 3-wire serial interface which can be operated at clock rates up to 50MHz. Daisychain capability and a hardware CLR function are included. The LTC2600/LTC2610/LTC2620 incorporate a power-on reset circuit. During power-up, the voltage outputs rise less than 10mV above zero-scale; and after power-up, they stay at zero-scale until a valid write and update take place.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
n n n n n n n n n
Smallest Pin-Compatible Octal DACs: LTC2600: 16 Bits LTC2610: 14 Bits LTC2620: 12 Bits Guaranteed 16-Bit Monotonic Over Temperature Wide 2.5V to 5.5V Supply Range Low Power Operation: 250A per DAC at 3V Individual Channel Power-Down to 1A, Max Ultralow Crosstalk Between DACs (<10V) High Rail-to-Rail Output Drive (15mA, Min) Double-Buffered Digital Inputs Pin-Compatible 10-/8-Bit Versions (LTC1660/LTC1665) Tiny 16-Lead Narrow SSOP and 20-Lead 4mm x 5mm QFN Packages
APPLICATIONS
n n n n
Mobile Communications Process Control and Industrial Automation Instrumentation Automatic Test Equipment
BLOCK DIAGRAM
(20) GND 1 REGISTER REGISTER REGISTER REGISTER 16 VCC (17) (1) VOUTA 2 DAC A DAC H 15 VOUTH (16)
Differential Nonlinearity (LTC2600)
REGISTER REGISTER REGISTER REGISTER (2) VOUTB 3 DAC B DAC G 14 VOUTG (15) 1.0 0.8 0.6 REGISTER REGISTER REGISTER REGISTER 0.4 DNL (LSB) DAC F 13 VOUTF (14) 0.2 0 -0.2 -0.4 -0.6 -0.8 (5) REF 6 CONTROL LOGIC DECODE 10 SDO (10) POWER-ON RESET 11 CLR (11) -1.0 0 16384 32768 CODE 49152 65535
2600 G21
VCC = 5V VREF = 4.096V
(3) VOUTC
4
DAC C
REGISTER
REGISTER
REGISTER
(4) V OUTD
REGISTER
5
DAC D
DAC E
12 VOUTE
(13)
(7) CS/LD
7
(8)
SCK
8
32-BIT SHIFT REGISTER
9
SDI
2600 BD
(9)
NOTE: NUMBERS IN PARENTHESIS REFER TO THE UFD PACKAGE
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LTC2600/LTC2610/LTC2620 ABSOLUTE MAXIMUM RATINGS
(Note 1)
Any Pin to GND ........................................... -0.3V to 6V Any Pin to VCC ............................................ -6V to 0.3V Operating Temperature Range LTC2600C/LTC2610C/LTC2620C ............. 0C to 70C LTC2600I/LTC2610I/LTC2620I............. -40C to 85C
Storage Temperature Range.................. -65C to 150C Maximum Junction Temperature........................... 125C Lead Temperature (Soldering, 10 sec) ................. 300C
PIN CONFIGURATION
TOP VIEW GND DNC DNC TOP VIEW GND VOUTA VOUTB VOUTC VOUTD REF CS/LD SCK 1 2 3 4 5 6 7 8 16 VCC 15 VOUTH 14 VOUTG 13 VOUTF 12 VOUTE 11 CLR 10 SDO 9 SDI VOUTA 1 VOUTB 2 VOUTC 3 VOUTD 4 REF 5 DNC 6 7 CS/LD 8 SCK 9 10 SDI SDO 21 VCC 16 VOUTH 15 VOUTG 14 VOUTF 13 VOUTE 12 DNC 11 CLR 20 19 18 17
GN PACKAGE 16-LEAD PLASTIC SSOP TJMAX = 125C, JA = 150C/W
UFD PACKAGE 20-LEAD (4mm 5mm) PLASTIC QFN TJMAX = 150C, JA = 43C/W EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH LTC2600CUFD#PBF LTC2600IUFD#PBF LTC2600CGN#PBF LTC2600IGN#PBF LTC2610CUFD#PBF LTC2610IUFD#PBF LTC2610CGN#PBF LTC2610IGN#PBF LTC2620CUFD#PBF LTC2620IUFD#PBF LTC2620CGN#PBF LTC2620IGN#PBF TAPE AND REEL LTC2600CUFD#TRPBF LTC2600IUFD#TRPBF LTC2600CGN#TRPBF LTC2600IGN#TRPBF LTC2610CUFD#TRPBF LTC2610IUFD#TRPBF LTC2610CGN#TRPBF LTC2610IGN#TRPBF LTC2620CUFD#TRPBF LTC2620IUFD#TRPBF LTC2620CGN#TRPBF LTC2620IGN#TRPBF PART MARKING* 2600 2600 2600 2600I 2610 2610 2610 2610I 2620 2620 2620 2620I PACKAGE DESCRIPTION 20-Lead (4mm x 5mm) Plastic DFN 20-Lead (4mm x 5mm) Plastic DFN 16-Lead Plastic SSOP 16-Lead Plastic SSOP 20-Lead (4mm x 5mm) Plastic DFN 20-Lead (4mm x 5mm) Plastic DFN 16-Lead Plastic SSOP 16-Lead Plastic SSOP 20-Lead (4mm x 5mm) Plastic DFN 20-Lead (4mm x 5mm) Plastic DFN 16-Lead Plastic SSOP 16-Lead Plastic SSOP TEMPERATURE RANGE 0C to 70C -40C to 85C 0C to 70C -40C to 85C 0C to 70C -40C to 85C 0C to 70C -40C to 85C 0C to 70C -40C to 85C 0C to 70C -40C to 85C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
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LTC2600/LTC2610/LTC2620 ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER DC Performance Resolution Monotonicity DNL INL Differential Nonlinearity Integral Nonlinearity Load Regulation VCC = 5V, VREF = 4.096V (Note 2) VCC = 5V, VREF = 4.096V (Note 2) VCC = 5V, VREF = 4.096V (Note 2) VREF = VCC = 5V, Mid-Scale IOUT = 0mA to 15mA Sourcing IOUT = 0mA to 15mA Sinking VREF = VCC = 2.5V, Mid-Scale IOUT = 0mA to 7.5mA Sourcing IOUT = 0mA to 7.5mA Sinking ZSE VOS Zero-Scale Error Offset Error VOS Temperature Coefficient GE Gain Error Gain Temperature Coefficient VCC = 5V, VREF = 4.096V VCC = 5V, VREF = 4.096V Code = 0 VCC = 5V, VREF = 4.096V (Note 7)
l l l l l l l l
The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 2.5V to 5.5V, VREF VCC, VOUT unloaded, unless otherwise noted.
CONDITIONS MIN 12 12 0.5 0.75 4 3 0.1 0.1 0.2 0.2 1 1 3 0.7 0.2 6.5 0.7 LTC2620 TYP MAX MIN 14 14 1 16 0.5 0.5 1 1 9 9 12 0.3 0.3 0.8 0.8 1 1 3 0.2 6.5 0.7 LTC2610 TYP MAX MIN 16 16 1 64 2 2 4 4 9 9 LTC2600 TYP MAX UNITS Bits Bits LSB LSB LSB/mA LSB/mA LSB/mA LSB/mA mV mV V/C %FSR ppm/C
0.025 0.125 0.025 0.125 0.05 0.05 1 1 3 0.2 6.5 0.25 0.25 9 9
The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 2.5V to 5.5V, VREF VCC, VOUT unloaded, unless otherwise noted.
SYMBOL PARAMETER PSR ROUT Power Supply Rejection DC Output Impedance DC Crosstalk (Note 4) CONDITIONS VCC = 10%
l VREF = VCC = 5V, Mid-Scale; -15mA IOUT 15mA VREF = VCC = 2.5V, Mid-Scale; -7.5mA IOUT 7.5mA l
LTC2600/LTC2610/LTC2620 MIN TYP MAX -80 0.025 0.030 10 3.5 7.3
l l l l l
UNITS dB V V/mA V
0.15 0.15
Due to Full-Scale Output Change (Note 5) Due to Load Current Change Due to Powering Down (per Channel) VCC = 5.5V, VREF = 5.6V Code: Zero-Scale; Forcing Output to VCC Code: Full-Scale; Forcing Output to GND VCC = 2.5V, VREF = 5.6V Code: Zero-Scale; Forcing Output to VCC Code: Full-Scale; Forcing Output to GND 15 15 7.5 7.5 0 11
ISC
Short-Circuit Output Current
34 34 18 24
60 60 50 50 VCC
mA mA mA mA V k pF A
Reference Input Input Voltage Range Resistance Capacitance IREF Reference Current, Power-Down Mode All DACs Powered Down
l
Normal Mode
l
16 90 0.001
20 1
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LTC2600/LTC2610/LTC2620 ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER Power Supply VCC ICC Positive Supply Voltage Supply Current VCC = 5V (Note 3) VCC = 3V (Note 3) All DACs Powered Down (Note 3) VCC = 5V All DACs Powered Down (Note 3) VCC = 3V VCC = 2.5V to 5.5V VCC = 2.5V to 3.6V VCC = 4.5V to 5.5V VCC = 2.5V to 5.5V Load Current = -100A Load Current = +100A VIN = GND to VCC (Note 6)
l l l l l l l l l l VCC - 0.4 l l l
The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 2.5V to 5.5V, VREF VCC, VOUT unloaded, unless otherwise noted.
CONDITIONS LTC2600/LTC2610/LTC2620 MIN TYP MAX 2.5 2.6 2.0 0.35 0.10 2.4 2.0 0.8 0.6 0.4 1 8 5.5 4 3.2 1 1 UNITS V mA mA A A V V V V V V A pF
Digital I/O VIH VIL VOH VOL ILK CIN Digital Input High Voltage Digital Input Low Voltage Digital Output High Voltage Digital Output Low Voltage Digital Input Leakage Digital Input Capacitance
The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 2.5V to 5.5V, VREF VCC, VOUT unloaded, unless otherwise noted.
SYMBOL PARAMETER AC Performance tS Settling Time (Note 8) 0.024% (1LSB at 12 Bits) 0.006% (1LSB at 14 Bits) 0.0015% (1LSB at 16 Bits) 0.024% (1LSB at 12 Bits) 0.006% (1LSB at 14 Bits) 0.0015% (1LSB at 16 Bits) 7 7 9 2.7 4.8 0.80 1000 12 180 120 100 15 7 9 10 2.7 4.8 5.2 0.80 1000 12 180 120 100 15 s s s s s V/s pF nV * s kHz nV/Hz nV/Hz VP-P CONDITIONS MIN LTC2620 TYP MAX MIN LTC2610 TYP MAX MIN LTC2600 TYP MAX UNITS
Settling Time for 1LSB Step (Note 9) Voltage Output Slew Rate Capacitive Load Driving Glitch Impulse Multiplying Bandwidth en Output Voltage Noise Density Output Voltage Noise
2.7
0.80 1000 At Mid-Scale Transition At f = 1kHz At f = 10kHz 0.1Hz to 10Hz 12 180 120 100 15
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LTC2600/LTC2610/LTC2620 TIMING CHARACTERISTICS
SYMBOL PARAMETER VCC = 2.5V to 5.5V t1 t2 t3 t4 t5 t6 t7 t8 SDI Valid to SCK Setup SDI Valid to SCK Hold SCK High Time SCK Low Time CS/LD Pulse Width LSB SCK High to CS/LD High CS/LD Low to SCK High SDO Propagation Delay from SCK Falling Edge CLOAD = 10pF VCC = 4.5V to 5.5V VCC = 2.5V to 5.5V
l l l l l l l l l l l l
The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (See Figure 1) (Note 6)
CONDITIONS LTC2600/LTC2610/LTC2620 MIN TYP MAX 4 4 9 9 10 7 7 20 45 20 7 50 UNITS ns ns ns ns ns ns ns ns ns ns ns MHz
t9 t10
CLR Pulse Width CS/LD High to SCK Positive Edge SCK Frequency 50% Duty Cycle
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Linearity and monotonicity are defined from code kL to code 2N - 1, where N is the resolution and kL is given by kL = 0.016(2N/VREF), rounded to the nearest whole code. For VREF = 4.096V and N = 16, kL = 256 and linearity is defined from code 256 to code 65,535. Note 3: Digital inputs at 0V or VCC. Note 4: DC crosstalk is measured with VCC = 5V and VREF = 4.096V, with the measured DAC at mid-scale, unless otherwise noted.
Note 5: RL = 2k to GND or VCC. Note 6: Guaranteed by design and not production tested. Note 7: Inferred from measurement at code 256 (LTC2600), code 64 (LTC2610) or code 16 (LTC2620), and at full-scale. Note 8: VCC = 5V, VREF = 4.096V. DAC is stepped 1/4-scale to 3/4-scale and 3/4-scale to 1/4-scale. Load is 2k in parallel with 200pF to GND. Note 9: VCC = 5V, VREF = 4.096V. DAC is stepped 1LSB between halfscale and half-scale - 1. Load is 2k in parallel with 200pF to GND.
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LTC2600/LTC2610/LTC2620 TYPICAL PERFORMANCE CHARACTERISTICS
LTC2600 Integral Nonlinearity (INL)
32 24 16 DNL (LSB) INL (LSB) 8 0 -8 -16 -24 -32 0 16384 32768 CODE 49152 65535
2600 G20
Differential Nonlinearity (DNL)
1.0 0.8 0.6 0.4 INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 16384 32768 CODE 49152 65535
2600 G21
INL vs Temperature
32 24 16 8 0 -8 -16 -24 -32 -50 -30 -10 10 30 50 TEMPERATURE (C) 70 90 INL (NEG) INL (POS) VCC = 5V VREF = 4.096V
VCC = 5V VREF = 4.096V
VCC = 5V VREF = 4.096V
2600 G22
DNL vs Temperature
1.0 0.8 0.6 0.4 DNL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 -50 -30 -10 10 30 50 TEMPERATURE (C) 70 90 DNL (NEG) VCC = 5V VREF = 4.096V DNL (POS) INL (LSB) 32 24 16
INL vs VREF
1.5 VCC = 5.5V 1.0 INL (POS) DNL (LSB) 0.5
DNL vs VREF
VCC = 5.5V
8 0 -8 -16 -24 -32 0 1
DNL (POS) 0 DNL (NEG) -0.5 -1.0 -1.5
INL (NEG)
2 3 VREF (V)
4
5
2600 G24
0
1
2 3 VREF (V)
4
5
2600 G25
2600 G23
Settling to 1LSB
Settling of Full-Scale Step
VOUT 100V/DIV 9.7s CS/LD 2V/DIV
2600 G26
VOUT 100V/DIV
12.3s
CS/LD 2V/DIV
2600 G27
2s/DIV VCC = 5V, VREF = 4.096V 1/4-SCALE TO 3/4-SCALE STEP RL = 2k, CL = 200pF AVERAGE OF 2048 EVENTS
5s/DIV SETTLING TO 1LSB VCC = 5V, VREF = 4.096V CODE 512 TO 65535 STEP RL = 2k, CL = 200pF AVERAGE OF 2048 EVENTS
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LTC2600/LTC2610/LTC2620 TYPICAL PERFORMANCE CHARACTERISTICS
LTC2610 Integral Nonlinearity (INL)
8 6 4 DNL (LSB) INL (LSB) 2 0 -2 -4 -6 -8 0 4096 8192 CODE 12288 16383
2600 G28
Differential Nonlinearity (DNL)
1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 4096 8192 CODE 12288 16383
2600 G29
Settling to 1LSB
VCC = 5V VREF = 4.096V
VCC = 5V VREF = 4.096V
VOUT 100V/DIV
CS/LD 2V/DIV
8.9s 2s/DIV VCC = 5V, VREF = 4.096V 1/4-SCALE TO 3/4-SCALE STEP RL = 2k, CL = 200pF AVERAGE OF 2048 EVENTS
2600 G30
LTC2620 Integral Nonlinearity (INL)
2.0 1.5 1.0 DNL (LSB) INL (LSB) 0.5 0 -0.5 -1.0 -1.5 -2.0 0 1024 2048 CODE 3072 4095
2600 G31
Differential Nonlinearity (DNL)
1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 1024 2048 CODE 3072 4095
2600 G32
Settling to 1LSB
VCC = 5V VREF = 4.096V
VCC = 5V VREF = 4.096V 6.8s VOUT 1mV/DIV
CS/LD 2V/DIV
2600 G33
2s/DIV VCC = 5V, VREF = 4.096V 1/4-SCALE TO 3/4-SCALE STEP RL = 2k, CL = 200pF AVERAGE OF 2048 EVENTS
LTC2600/LTC2610/LTC2620 Current Limiting
0.10 0.08 0.06 0.04 VOUT (V) 0.02 0 -0.02 -0.04 -0.06 -0.08 -0.10 10 -40 -30 -20 -10 0 IOUT (mA) 20 30 40 VREF = VCC = 3V VREF = VCC = 5V CODE = MIDSCALE VREF = VCC = 5V VREF = VCC = 3V VOUT (mV) 1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 -35 -25 -15 -5 5 IOUT (mA) 15 25 35 -3 -50 -30 -10 10 30 50 TEMPERATURE (C) 70 90 VREF = VCC = 3V -2 VREF = VCC = 5V OFFSET ERROR (mV)
2600 G02
Load Regulation
CODE = MIDSCALE 3 2 1 0 -1
Offset Error vs Temperature
2600 G01
2600 G03
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LTC2600/LTC2610/LTC2620 TYPICAL PERFORMANCE CHARACTERISTICS
LTC2600/LTC2610/LTC2620 Zero-Scale Error vs Temperature
3 2.5 ZERO-SCALE ERROR (mV) GAIN ERROR (%FSR) 2.0 1.5 1.0 0.5 0 -50 0.4 0.3 OFFSET ERROR (mV) -30 -10 10 30 50 TEMPERATURE (C) 70 90 0.2 0.1 0 -0.1 -0.2 -0.3 -30 -10 10 30 50 TEMPERATURE (C) 70 90 -0.4 -50 -2 -3 2.5
Gain Error vs Temperature
3 2 1 0 -1
Offset Error vs VCC
3
3.5
4 VCC (V)
4.5
5
5.5
2600 G06
2600 G04
2600 G05
0.4 0.3 0.2 GAIN ERROR (%FSR) 0.1
Gain Error vs VCC
450 400 350 300 ICC (nA) 250 200 150
ICC Shutdown vs VCC
Large-Signal Response
0 -0.1 -0.2
VOUT 0.5V/DIV
VREF = VCC = 5V 1/4-SCALE TO 3/4-SCALE 2.5s/DIV
2600 G09
100 -0.3 -0.4 2.5 50 3 3.5 4 VCC (V) 4.5 5 5.5
2600 G07
0 2.5
3
3.5
4 VCC (V)
4.5
5
5.5
2600 G08
Mid-Scale Glitch Impulse
Power-On Reset Glitch
5.0 4.5 4.0
Headroom at Rails vs Output Current
5V SOURCING
VOUT 10mV/DIV 12nV-s TYP
VOUT (V)
VCC 1V/DIV 4mV PEAK 4mV PEAK
3.5 3.0 2.5 2.0 1.5 1.0 250s/DIV
2600 G11
3V SOURCING
CS/LD 5V/DIV 2.5s/DIV
2600 G10
VOUT 10mV/DIV
5V SINKING 3V SINKING
0.5 0 0 1 2 3
456 IOUT (mA)
7
8
9
10
2600 G12
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LTC2600/LTC2610/LTC2620 TYPICAL PERFORMANCE CHARACTERISTICS
LTC2600/LTC2610/LTC2620 Supply Current vs Logic Voltage
2.4 2.3 2.2 2.1 ICC (mA) 2.0 1.9 1.8 1.7 1.6 1.5 0 0.5 1 1.5 2 2.5 3 3.5 LOGIC VOLTAGE (V) 4 4.5 5 2.5s/DIV
2600 G14
Exiting Power-Down to Mid-Scale
VCC = 5V VREF = 2V VOUT 0.5V/DIV DACs A TO G IN POWER-DOWN MODE CS/LD 5V/DIV CLR 5V/DIV VOUT 1V/DIV
Hardware CLR
VCC = 5V SWEEP SCK, SDI AND CS/LD 0V TO VCC
1s/DIV
2600 G15
2600 G13
Multiplying Bandwidth
0 -3 -6 -9 -12 -15 dB -18 -21 -24 -27 -30 -33 -36 1k VCC = 5V VREF (DC) = 2V VREF (AC) = 0.2VP-P CODE = FULL SCALE 10k 100k FREQUENCY (Hz) 1M
2600 G16
Output Voltage Noise, 0.1Hz to 10Hz
VOUT 10V/DIV
0
1
2
3
456 SECONDS
7
8
9
10
2600 G17
Short-Circuit Output Current vs VOUT (Sinking)
0mA
Short-Circuit Output Current vs VOUT (Sourcing)
10mA/DIV
0mA
VCC = 5.5V 1V/DIV VREF = 5.6V CODE = 0 VOUT SWEPT 0V TO VCC
10mA/DIV
2600 G18
1V/DIV VCC = 5.5V VREF = 5.6V CODE = FULL SCALE VOUT SWEPT VCC TO 0V
2600 G19
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LTC2600/LTC2610/LTC2620 PIN FUNCTIONS
(GN/UFD)
GND (Pin 1/Pin 20): Analog Ground. VOUTA to VOUTH (Pins 2-5 and 12-15/Pins 1-48 and 13-16): DAC Analog Voltage Outputs. The output range is 0 - VREF. REF (Pin 6/Pin 5): Reference Voltage Input. 0V VREF VCC. CS/LD (Pin 7/Pin 7): Serial Interface Chip Select/Load Input. When CS/LD is low, SCK is enabled for shifting data on SDI into the register. When CS/LD is taken high, SCK is disabled and the specified command (see Table 1) is executed. SCK (Pin 8/Pin 8): Serial Interface Clock Input. CMOS and TTL compatible. SDI (Pin 9/Pin 9): Serial Interface Data Input. Data is applied to SDI for transfer to the device at the rising edge of SCK. The LTC2600, LTC2610 and LTC2620 accept input word lengths of either 24 or 32 bits.
SDO (Pin 10/Pin 10): Serial Interface Data Output. This pin is used for daisychain operation. The serial output of the shift register appears at the SDO pin. The data transferred to the device via the SDI pin is delayed 32 SCK rising edges before being output at the next falling edge. SDO is an active output and does not go high impedance, even when CS/LD is taken to a logic high level. CLR (Pin 11/Pin 11): Asynchronous Clear Input. A logic low at this level-triggered input clears all registers and causes the DAC voltage outputs to drop to 0V. CMOS and TTL compatible. VCC (Pin 16/Pin 17): Supply Voltage Input. 2.5V VCC 5.5V. DNC (Pins 6, 12, 18, 19 UFD Only): Do Not Connect. Exposed Pad (Pin 21 UFD Only): Ground. The exposed pad must be soldered to the PCB.
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LTC2600/LTC2610/LTC2620 BLOCK DIAGRAM
(20) GND 1 DAC REGISTER INPUT REGISTER INPUT REGISTER DAC REGISTER 16 VCC (17)
(1)
VOUTA
2
DAC A
DAC H
15 VOUTH
(16)
INPUT REGISTER
DAC REGISTER
INPUT REGISTER
(2)
VOUTB
3
DAC B
DAC REGISTER
DAC G
14 VOUTG
(15)
INPUT REGISTER
DAC REGISTER
INPUT REGISTER
(3)
VOUTC
DAC REGISTER
4
DAC C
DAC F
13 VOUTF
(14)
INPUT REGISTER
DAC REGISTER
INPUT REGISTER
(4)
DAC REGISTER
VOUTD
5
DAC D
DAC E
12 VOUTE
(13)
(5)
REF
6 CONTROL LOGIC DECODE
POWER-ON RESET
11
CLR
(11)
(7)
CS/LD
7
10
SDO
(10)
(8)
SCK
8
32-BIT SHIFT REGISTER
9
SDI
2600 BD02
(9)
NOTE: NUMBERS IN PARENTHESIS REFER TO THE UFD PACKAGE
TIMING DIAGRAM
t1 t2 SCK 1 t3 2 t4 3 23 t6 24 t10 SDI t5 CS/LD t8 SDO
2600 F01
t7
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LTC2600/LTC2610/LTC2620 OPERATION
Power-On Reset The LTC2600/LTC2610/LTC2620 clear the outputs to zero-scale when power is first applied, making system initialization consistent and repeatable. For some applications, downstream circuits are active during DAC power-up, and may be sensitive to nonzero outputs from the DAC during this time. The LTC2600/2610/2620 contain circuitry to reduce the power-on glitch: the analog outputs typically rise less than 10mV above zero-scale during power on if the power supply is ramped to 5V in 1ms or more. In general, the glitch amplitude decreases as the power supply ramp time is increased. See Power-On Reset Glitch in the Typical Performance Characteristics section. Power Supply Sequencing The voltage at REF (Pin 6) should be kept within the range -0.3V VREF VCC + 0.3V (see Absolute Maximum Ratings). Particular care should be taken to observe these limits during power supply turn-on and turn-off sequences, when the voltage at VCC (Pin 16) is in transition. Transfer Function The digital-to-analog transfer function is: k VOUT(IDEAL) = N VREF 2 where k is the decimal equivalent of the binary DAC input code, N is the resolution and VREF is the voltage at REF (Pin 6).
Table 1.
COMMAND* C3 0 0 0 0 0 1 C2 0 0 0 0 1 1 C1 0 0 1 1 0 1 C0 0 1 0 1 0 1 Write to Input Register n Update (Power Up) DAC Register n Write to Input Register n, Update (Power Up) All n Write to and Update (Power Up) n Power Down n No Operation
Serial Interface The CS/LD input is level triggered. When this input is taken low, it acts as a chip-select signal, powering on the SDI and SCK buffers and enabling the input shift register. Data (SDI input) is transferred at the next 24 rising SCK edges. The 4-bit command, C3-C0, is loaded first; then the 4-bit DAC address, A3-A0; and finally the 16-bit data word. The data word comprises the 16-, 14- or 12-bit input code, ordered MSB-to-LSB, followed by 0, 2 or 4 don't-care bits (LTC2600, LTC2610 and LTC2620 respectively). Data can only be transferred to the device when the CS/LD signal is low.The rising edge of CS/LD ends the data transfer and causes the device to carry out the action specified in the 24-bit input word. The complete sequence is shown in Figure 2a. The command (C3-C0) and address (A3-A0) assignments are shown in Table 1. The first four commands in the table consist of write and update operations. A write operation loads a 16-bit data word from the 32-bit shift register into the input register of the selected DAC, n. An update operation copies the data word from the input register to the DAC register. Once copied into the DAC register, the data word becomes the active 16-, 14- or 12-bit input code, and is converted to an analog voltage at the DAC output. The update operation also powers up the selected DAC if it had been in power-down mode. The data path and registers are shown in the Block Diagram. While the minimum input word is 24 bits, it may optionally be extended to 32 bits. To use the 32-bit word width, 8 don't-care bits are transferred to the device first, followed by the 24-bit word as just described. Figure 2b shows the
ADDRESS (n)* A3 0 0 0 0 0 0 0 0 1 A2 0 0 0 0 1 1 1 1 1 A1 0 0 1 1 0 0 1 1 1 A0 0 1 0 1 0 1 0 1 1 DAC A DAC B DAC C DAC D DAC E DAC F DAC G DAC H All DACs
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*Command and address codes not shown are reserved and should not be used.
12
LTC2600/LTC2610/LTC2620 OPERATION
INPUT WORD (LTC2600)
COMMAND C3 C2 C1 C0 A3 ADDRESS A2 A1 A0 DATA (16 BITS) D15 D14 D13 D12 D11 D10 D9 MSB D8 D7 D6 D5 D4 D3 D2 D1 D0 LSB
2600 TBL01
INPUT WORD (LTC2610)
COMMAND C3 C2 C1 C0 A3 ADDRESS A2 A1 A0 DATA (14 BITS + 2 DON'T-CARE BITS) D13 D12 D11 D10 D9 MSB D8 D7 D6 D5 D4 D3 D2 D1 D0 LSB
2600 TBL02
X
X
INPUT WORD (LTC2620)
COMMAND C3 C2 C1 C0 A3 ADDRESS A2 A1 A0 D11 D10 D9 MSB DATA (12 BITS + 4 DON'T-CARE BITS) D8 D7 D6 D5 D4 D3 D2 D1 D0 LSB
2600 TBL03
X
X
X
X
32-bit sequence. The 32-bit word is required for daisychain operation, and is also available to accommodate microprocessors which have a minimum word width of 16 bits (2 bytes). Daisychain Operation The serial output of the shift register appears at the SDO pin. Data transferred to the device from the SDI input is delayed 32 SCK rising edges before being output at the next SCK falling edge. The SDO output can be used to facilitate control of multiple serial devices from a single 3-wire serial port (i.e., SCK, SDI and CS/LD). Such a "daisychain" series is configured by connecting SDO of each upstream device to SDI of the next device in the chain. The shift registers of the devices
are thus connected in series, effectively forming a single input shift register which extends through the entire chain. Because of this, the devices can be addressed and controlled individually by simply concatenating their input words; the first instruction addresses the last device in the chain and so forth. The SCK and CS/LD signals are common to all devices in the series. In use, CS/LD is first taken low. Then the concatenated input data is transferred to the chain, using SDI of the first device as the data input. When the data transfer is complete, CS/LD is taken high, completing the instruction sequence for all devices simultaneously. A single device can be controlled by using the no-operation command (1111) for the other devices in the chain.
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13
LTC2600/LTC2610/LTC2620 OPERATION
Power-Down Mode For power-constrained applications, power-down mode can be used to reduce the supply current whenever less than eight outputs are needed. When in power-down, the buffer amplifiers and reference inputs are disabled, and draw essentially zero current. The DAC outputs are put into a high impedance state, and the output pins are passively pulled to ground through individual 90k resistors. When all eight DACs are powered down, the master bias generation circuit is also disabled. Input- and DAC-register contents are not disturbed during power-down. Any channel or combination of channels can be put into power-down mode by using command 0100b in combination with the appropriate DAC address, (n). The 16-bit data word is ignored. The supply and reference currents are reduced by approximately 1/8 for each DAC powered down; the effective resistance at REF (Pin 6) rises accordingly, becoming a high impedance input (typically > 1G) when all eight DACs are powered down. Normal operation can be resumed by executing any command which includes a DAC update, as shown in Table 1. The selected DAC is powered up as its voltage output is updated. There is an initial delay as the DAC powers up before it begins its usual settling behavior. If less than eight DACs are in a powered-down state prior to the update command, the power-up delay is 5s. If, on the other hand, all eight DACs are powered down, then the master bias generation circuit is also disabled and must be restarted. In this case, the power-up delay is greater: 12s for VCC = 5V, 30s for VCC = 3V. Voltage Outputs Each of the 8 rail-to-rail amplifiers contained in these parts has guaranteed load regulation when sourcing or sinking up to 15mA at 5V (7.5mA at 3V). Load regulation is a measure of the amplifier's ability to maintain the rated voltage accuracy over a wide range of load conditions. The measured change in output voltage per milliampere of forced load current change is expressed in LSB/mA. DC output impedance is equivalent to load regulation, and may be derived from it by simply calculating a change in units from LSB/mA to Ohms. The amplifiers' DC output impedance is 0.025 when driving a load well away from the rails. When drawing a load current from either rail, the output voltage headroom with respect to that rail is limited by the 25 typical channel resistance of the output devices; e.g., when sinking 1mA, the minimum output voltage = 25 * 1mA = 25mV. See the graph Headroom at Rails vs Output Current in the Typical Performance Characteristics section. The amplifiers are stable driving capacitive loads of up to 1000pF . Board Layout The excellent load regulation and DC crosstalk performance of these devices is achieved in part by keeping "signal" and "power" grounds separated internally and by reducing shared internal resistance to just 0.005.
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14
LTC2600/LTC2610/LTC2620 OPERATION
The GND pin functions both as the node to which the reference and output voltages are referred and as a return path for power currents in the device. Because of this, careful thought should be given to the grounding scheme and board layout in order to ensure rated performance. The PC board should have separate areas for the analog and digital sections of the circuit. This keeps digital signals away from sensitive analog signals and facilitates the use of separate digital and analog ground planes which have minimal capacitive and resistive interaction with each other. Digital and analog ground planes should be joined at only one point, establishing a system star ground as close to the device's ground pin as possible. Ideally, the analog ground plane should be located on the component side of the board, and should be allowed to run under the part to shield it from noise. Analog ground should be a continuous and uninterrupted plane, except for necessary lead pads and vias, with signal traces on another layer. The GND pin of the part should be connected to analog ground. Resistance from the GND pin to system star ground should be as low as possible. Resistance here will add directly to the effective DC output impedance of the device (typically 0.025), and will degrade DC crosstalk. Note that the LTC2600/LTC2610/LTC2620 are no more susceptible to these effects than other parts of their type; on the contrary, they allow layout-based performance improvements to shine rather than limiting attainable performance with excessive internal resistance. Rail-to-Rail Output Considerations In any rail-to-rail voltage output device, the output is limited to voltages within the supply range. Since the analog outputs of the device cannot go below ground, they may limit for the lowest codes as shown in Figure 3b. Similarly, limiting can occur near full scale when the REF pin is tied to VCC. If VREF = VCC and the DAC full-scale error (FSE) is positive, the output for the highest codes limits at VCC as shown in Figure 3c. No full-scale limiting can occur if VREF is less than VCC - FSE. Offset and linearity are defined and tested over the region of the DAC transfer function where no output limiting can occur.
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15
OPERATION
LTC2600/LTC2610/LTC2620
16
1 2 7 13 14 17 D7
YYYY F02a
CS/LD 3 4 10 21 D3 D2 D1 D0 23 D14 DATA WORD D13 D12 D11 D10 D9 D8 D6 D5 D4 11 12 18 24 16 20 22 C0 ADDRESS WORD A3 A2 A1 A0 D15 5 6 8 9 15 19 C1
SCK C2 COMMAND WORD
SDI
C3
24-BIT INPUT WORD
Figure 2a. LTC2600 24-Bit Load Sequence (Minimum Input Word). LTC2610 SDI Data Word: 14-Bit Input Code + 2 Don't-Care Bits; LTC2620 SDI Data Word: 12-Bit Input Code + 4 Don't-Care Bits
CS/LD 6 7 13 14 17 D15 D14 D13 D12 D11 D10 A2 ADDRESS WORD C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 A1 A0 A3 X COMMAND WORD X X X C3 C2 C1 X C3 C2 C1 C0 8 9 10 21 11 12 18 16 20 15 19 X 22 23 D9 24 D8 25 D7 DATA WORD D8 D7 D6 D5 D4 D3 D2 D1 D0 26 D6 27 D5 28 D4 29 D3 30 D2 31 D1 32 D0
SCK
1
2
3
4
5
SDI
X
X
X
X
X
DON'T CARE
SDO
X
X
X
X
X
PREVIOUS 32-BIT INPUT WORD t1 t2 SCK SDI SDO 17 t3 D15 t8 PREVIOUS D15 PREVIOUS D14 t4 D14 18
CURRENT 32-BIT INPUT WORD
YYYY F02b
Figure 2b. LTC2600 32-Bit Load Sequence (Required for Daisy-Chain Operation). LTC2610 SDI/SDO Data Word: 14-Bit Input Code + 2 Don't-Care Bits; LTC2620 SDI/SDO Data Word: 12-Bit Input Code + 4 Don't-Care Bits
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LTC2600/LTC2610/LTC2620 OPERATION
VREF = VCC POSITIVE FSE
VREF = VCC
OUTPUT VOLTAGE
OUTPUT VOLTAGE INPUT CODE (c) OUTPUT VOLTAGE 0 32, 768 INPUT CODE (a) 65, 535
0V NEGATIVE OFFSET INPUT CODE (b)
2600 F03
Figure 3. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative Offset for Codes Near Zero-Scale (c) Effect of Positive Full-Scale Error for Codes Near Full Scale
PACKAGE DESCRIPTION
GN Package 16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.045 .005 .189 - .196* (4.801 - 4.978) 16 15 14 13 12 11 10 9
.009 (0.229) REF
.254 MIN
.150 - .165 .229 - .244 (5.817 - 6.198) .150 - .157** (3.810 - 3.988)
.0165 .0015
.0250 BSC 1 .015 .004 x 45 (0.38 0.10) .0532 - .0688 (1.35 - 1.75) 23 4 56 7 8 .004 - .0098 (0.102 - 0.249)
RECOMMENDED SOLDER PAD LAYOUT
.007 - .0098 (0.178 - 0.249)
0 - 8 TYP
.016 - .050 (0.406 - 1.270) NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) 3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
.008 - .012 (0.203 - 0.305) TYP
.0250 (0.635) BSC
GN16 (SSOP) 0204
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17
LTC2600/LTC2610/LTC2620 PACKAGE DESCRIPTION
UFD Package 20-Lead Plastic QFN (4mm x 5mm)
(Reference LTC DWG # 05-08-1711 Rev B)
0.70
0.05
4.50
0.05 3.10
1.50 REF 0.05
2.65
0.05 3.65 0.05
PACKAGE OUTLINE
0.25 0.05 0.50 BSC 2.50 REF 4.10 0.05 5.50 0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4.00 0.10 (2 SIDES) PIN 1 TOP MARK (NOTE 6) 0.75 0.05 R = 0.05 TYP 1.50 REF 19 20 0.40 0.10 PIN 1 NOTCH R = 0.20 OR C = 0.35
1 2 5.00 0.10 (2 SIDES) 2.50 REF 3.65 0.10 2.65 0.10
(UFD20) QFN 0506 REV B
0.200 REF 0.00 - 0.05
R = 0.115 TYP
0.25
0.05
0.50 BSC
BOTTOM VIEW--EXPOSED PAD NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X). 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
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18
LTC2600/LTC2610/LTC2620 REVISION HISTORY
REV D E DATE 03/10 05/10 DESCRIPTION Revise GN Part Markings in Order Information Changed "No Connect" pins to "Do Not Connect" in Pin Configuration and Pin Functions sections
(Revision history begins at Rev D)
PAGE NUMBER 2 2, 10
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC2600/LTC2610/LTC2620 TYPICAL APPLICATION
Schematic for LTC2600 Demonstration Circuit DC579. The Outputs Are Measured by an Onboard LTC2428
1 TP1 4 3 2 1 VSS SDA A2 A1 A0 SCL WP VCC 5 6 7 8 C3 0.1F 1 VCC TP2 R1, R3, R4 R1 are 4.99k, 1% R3 R4 VREF C1 0.1F R2 7.5k 11 CLR C2 0.1F VCC VOUTA VOUTB SCK CS 14 12 10 8 6 4 2 + + + + + + + + + + + + + + 13 11 9 7 5 3 1 8 7 9 10 MOSI MISO 1 VIN VOUTC SCK LS/LD SDI SDO GND 1 TP16 U2 LTC2600CGN VOUTD VOUTE VOUTF VOUTG VOUTH 16 2 3 4 5 12 13 14 15 1 1 1 1 1 1 1 1 1 1 VCC
6 REF
U1 24LC025
TP3 DAC A TP4 DAC B TP5 DAC C TP6 DAC D TP7 DAC E TP8 DAC F TP9 DAC G TP10 DAC H C10 100pF 7 MUXOUT
TP14 GND TP15 GND
VREF
VCC
VCC
5V
J1 HD2X7
R5 7.5k R8 22 4 ADCIN 3 FSSET
C4 0.1F
C5 0.1F JP1 ON/OFF DISABLE ADC
3 2 2 8 1 VCC VCC
VIN 2
U4 LT1236ACS8-5 VIN GND C6 0.1F 4 VOUT 6 1 5V 4.096V 2 3 JP2 VREF VREF 9 1 C7 4.7F 6.3V TP11 VREF 10 11 12 13 14 15 6 1 5VREF C8 REGULATOR 1F 16V 2 3 JP3 VCC 5V VCC 1 1 TP12 VCC TP13 GND 17 5 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 ZSSET
CSADC CSMUX 4-/8-CHANNEL MUX + 20-BIT ADC - LTC2424/LTC2428 SCK CLK DIN SD0 FO GND GND GND GND GND GND GND 6 16 18 22 27 28
23 20 25 19 21 24 26 R7 7.5k
R6 7.5k
CS SCK
U5 LT1461ACS8-4 2 3 C9 0.1F VIN SHDN GND 4 VOUT
1 U3 LTC2428CG
RELATED PARTS
PART NUMBER LTC1458/LTC1458L LTC1654 LTC1655/LTC1655L LTC1657/LTC1657L LTC1660/LTC1665 LTC1821 DESCRIPTION Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality Dual 14-Bit Rail-to-Rail VOUT DAC Single 16-Bit VOUT DAC with Serial Interface in SO-8 Parrallel 5V/3V 16-Bit VOUT DAC Octal 10/8-Bit VOUT DAC in 16-Pin Narrow SSOP Parallel 16-Bit Voltage Output DAC COMMENTS LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.096V LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V Programmable Speed/Power, 3.5s/750A, 8s/450A VCC = 5V(3V), Low Power, Deglitched Low Power, Deglitched, Rail-to-Rail VOUT VCC = 2.7V to 5.5V, Micropower, Rail-to-Rail Output Precision 16-Bit Settling in 2s for 10V Step
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20 Linear Technology Corporation
(408) 432-1900 FAX: (408) 434-0507
LT 0510 REV E * PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2003

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